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Refer to the Material and Process Compatibility page for information on materials compatible with this tool.
Equipment Status
: Set as UP, PROBLEM, or DOWN, and report the issue date (MM/DD) and a brief description. Italicized fields will be filled in by BNC Staff in response to issues. See Problem Reporting Guide for more info.

StatusUP
Issue Date and Description


Estimated Fix Date and Comment

Responding Staff

/wiki/spaces/BNCWiki/pages/6236532


iLab Name: XeF2
iLab Kiosk: BRK Etch Core
FIC: Shared
Owner: Francis Manfred
Location:
Cleanroom - S Bay
Maximum Wafer Size:
4"/100 mm

Overview

General Description

The Xactix Xenon Difluroide E1 is an isotropic etch system, frequently used for MEMS applications. XeF2 etching shows extremely high selectivity of silicon to silicon dioxide, photoresist, silicon nitride, and aluminum. Etch rates depend on the amount of exposed silicon, so recipes will depend on a particular sample. Silicon based samples up to 4" may be used.

Specifications

Etch rates: Highly dependent on sample size, from ~10 μm/min for small samples to ~0.2 μm/min for whole 6" wafers.

Selectivity:
1000:1 (Thermal/Low Temperature SiO2:Si)
>1000:1 Si3N4:Si
Low attack (depending on conditions) for Gold, Copper, and Si

Nonreactive with:
Al, Ni, Cr, Pt, Ga
PZT, MgO, ZnO, AlN, GaAs,
Photoresists, PDMS, C4F8, Silica Glass, PVC dicing tape, PP, PEN, PET, ETFE, and Acrylic

Available in either pulsed or continuous flow

Technology Overview

XeF2 exists as solid crystals, and sublimates to form a vapor-phase etchant. The process is a dry, vacuum based process that proceeds spontaneously, and thus does not rely on a plasma or other chemical activation. It proceeds as an isotropic etch for silicon, molybdenus, and germanium. The XeF2 etching rate does not depend on crystal plane, or silicon dopant content. As the XeF2-Si reaction is exothermic, a delay step may be added to cool the wafer between etch cycles and minimize any thermal issues.

For silicon, the etch proceeds as:
2XeF2 + Si => 2Xe + SiF4

 

Sample Requirements and Preparation

For well controlled etching, a BOE dip should be done directly before XeF2 etching. XeF2 will etch SiO2 very slowly, so removing the native oxide layer will allow for a more uniform etch.

Whether the native oxide has been removed or not, all samples should be dehydrated directly prior to placement in etch chamber, either with IPA or a hotplate dehydration bake. The presence of adsorbed water on samples will result in the formation of both gaseous HF and a silicon flouride polymer on the sample surface. This polymer layer will reduce or completely stop etch progression, and will not be removed in either solvent soaks or O2 plasma.

Note: XeF2 will also etch Titanium, Titanium Nitride, Tantalum, Tantalum Nitride, and Tungsten at etch rates from 0-30 nm/min, strongly depending on the local temperature.

 

Standard Operating Procedure


Questions & Troubleshooting

How long should my cycle time be?
Cycle time should be set to allow all of the XeF2 vapor to react with exposed silicon. For large areas of exposed silicon, XeF2 will quickly react with the exposed areas, and the cycle time may be reduced. For a smaller chip, cycle times will need to somewhat longer to allow all of the XeF2 to react fully.

In order to tell that all XeF2 has reacted, the chamber pressure may be monitored. The etching reaction proceeds as 2XeF2 + Si -> SiF4 + 2Xe, meaning 2 moles of reactant gas will be present at the beginning of the etch step, and 3 will be present after the etch has completed. Therefore, the pressure in the chamber will increase somewhat while the etch is proceeding, and will level off after the etch has completed.

The etch rate on my sample seems nonuniform?
Uniformity is an inherent issue with XeF2 etching. There is a limited amount of etchant released in each cycle, and the local etch rate will depend on the amount of exposed silicon and available XeF2 vapor. In general, large exposed areas of silicon will show the worst uniformity, and regular patterns of small holes (with the rest of the wafer covered) will show the best uniformity. Minimizing unneeded exposed silicon will allow for faster and more uniform etching of the pattern.

 

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