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2024-12-20 to 2025-01-02: Reduced Holiday Operations

Dear Birck Research Community,

The Purdue winter recess begins effective Friday afternoon December 20th and concludes Thursday morning, January 2. The university is officially closed during this time. As we have done in past years, the Birck Nanotechnology Center will remain available for research but will be unstaffed and hazardous gasses will be unavailable. Lab work may otherwise proceed, though any fume hood work must be done with someone else present in the same laboratory or cleanroom bay (the "buddy" system). Click the link above to get more detail about equipment conditions and rules.


Refer to the Material and Process Compatibility page for information on materials compatible with this tool.
Equipment Status: Set as UP, PROBLEM, or DOWN, and report the issue date (MM/DD) and a brief description. Italicized fields will be filled in by BNC Staff in response to issues. See Problem Reporting Guide for more info.

StatusDOWN
Issue Date and Description

RF2 ICP Supply output is bad.

Estimated Fix Date and Comment

Will update with ETA when I have one that is reliable. Supply output not sufficient for deposition. Sent supply and match box to vender for expedited repair. New PSU estimated ship date is 4/25.

Responding StaffR. Hosler

 iLab Growth Kiosk

iLab Furnace Kiosk

Create PECVD-TA Log Entry

View PECVD-TA Logbook

Create a
Problem Ticket

View MSDS


iLab Name: Plasma-Therm APEX SLR HDPCVD
iLab Kiosk: BRK Growth Core
FIC: Shared
Owner: Rich Hosler
Location: Cleanroom - R Bay
Wafer Size: 4"/100 mm

Please inspect through the top window to see if any broken wafer bits are present before loading sample!


Only use recipes with "AR CLEAN" in the title on samples/wafers that are bare Silicon. The Argon clean process can etch structure and cause chamber contamination.

Note on Carrier Wafers

Please note that carrier wafers should not have gouges, debris, broken parts, or excessive deposition stress.

In this example the wafer became overstressed and slightly cracked, leaving debris in the chamber which caused damage to the ceramic plate when the cleaning wafer went in.

If you're unsure, send me a picture at hosler0@purdue.edu and I'll answer as quickly as possible.  

Overview

General Description

Fab Forum HDPCVD Presentation.pptx

Specifications

The system has following process gases:

  1. 100% Silane (SiH4)
  2. N2
  3. Ar
  4. CH4 Methane
  5. O2
  6. SF6 Sulfur Hexaflouride

Configured for 4" substrates.

  • Bias Supply RF power: 600W @ 13.56MHz
  • ICP RF Power: 1kW @ 2MHz
  • Electrode temp range: 10-180°C ±3°C


Technology Overview 

 

Sample Requirements and Preparation

  • All samples must be 4” wafers (bare or pocketed) or mounted onto a 4” wafer via Crystalbond or equivalent. 
  • Samples and wafers must be cleaned using the TAI (Toluene, Acetone, IPA) process followed by either Piranha or RCA cleaning as appropriate for sample compatibility.

Standard Operating Procedure


Process Library

Recipe

Precursors

Validated Substrates

Rate (Å/min)

RI (F40 measured)

Deposition Temp. Tested (°C)

Bias Power / ICP Power (W)

Pressure (mTorr)

SiO2

SiH­4 / O2 / Ar

Si and SiC

1000

1.46-1.50

170

25/900

8

SiNx

SiH4 / N2 / Ar

Si

1100

1.964-2.25

25-150

0/900

12.5

a:SiSiH4 / N2 / ArSi600tbd15080/6005

Chamber Etch

SF6 / O2 / Ar

Sapphire Wafer

70

n/a

178

10/1000 (750)

40


New Process Consultation: 

Plasma-Therm Technical Support (ask for process support)

E-mail: techsupport@plasmatherm.com
Phone: (800) 246-2592

References

References


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