Plasma-Therm Apex SLR HDPCVD

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iLab Name: Plasma-Therm APEX SLR HDPCVD Deposition System
iLab Kiosk: BRK Growth Core
FIC: Shared
Owner: Guannan Chen
Location: Cleanroom - R Bay
Wafer Size: 4"/100 mm

Please inspect through the top window to see if any broken wafer bits are present before loading sample!

Only use recipes with "AR CLEAN" in the title on samples/wafers that are bare Silicon. The Argon clean process can etch structure and cause chamber contamination.

Note on Carrier Wafers

Please note that carrier wafers should not have gouges, debris, broken parts, or excessive deposition stress.

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In this example the wafer became overstressed and slightly cracked, leaving debris in the chamber which caused damage to the ceramic plate when the cleaning wafer went in.

If you're unsure, send me a picture at chen6283@purdue.edu and I'll answer as quickly as possible.  

Overview

General Description

Fab Forum HDPCVD Presentation.pptx some info on this is out of date, SOP document overrides all information.

Specifications

The system has following process gases:

1. 100% Silane (SiH₄)

2. N₂

3. Ar

4. CH₄ Methane

5. O₂

6. SF₆ Sulfur Hexaflouride

Configured for 4" substrates.

• Bias Supply RF power: 600W @ 13.56MHz

• ICP RF Power: 1kW @ 2MHz

• Electrode temp range: 10-180°C ±3°C

Technology Overview 

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Sample Requirements and Preparation

• All samples must be 4” wafers (bare or pocketed) or use a 4" carrier wafer. 

• Samples and wafers must be cleaned using the TAI (Toluene, Acetone, IPA) process followed by either Piranha or RCA cleaning as appropriate for sample compatibility.

Standard Operating Procedure

Process Library

New Process Consultation: 

Plasma-Therm Technical Support (ask for process support)

E-mail: techsupport@plasmatherm.com
Phone: (800) 246-2592

References

• Silicon Nitride for MEMS Applications: LPCVD and PECVD Process Comparison

• DEVELOPMENT OF LOW TEMPERATURE SILICON NITRIDE AND SILICON OXIDE